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FEATURES Fast, Flexible, Microprocessor Interfacing in Serially Controlled Systems Buffered Digital Output Pin for Daisy-Chaining Multiple DACs Minimizes Address-Decoding in Multiple DAC Systems--Three-Wire Interface for Any Number of DACs One Data Line One CLK Line One Load Line Improved Resistance to ESD -40 C to +85 C for the Extended Industrial Temperature Range APPLICATIONS Multiple-Channel Data Acquisition Systems Process Control and Industrial Automation Test Equipment Remote Microprocessor-Controlled Systems GENERAL INFORMATION
12-Bit Serial Daisy-Chain CMOS D/A Converter DAC8143
FUNCTIONAL BLOCK DIAGRAM
VDD RFB
DAC8143
VREF 12-BIT D/A CONVERTER IOUT1 IOUT2 CLR LD1 LD2 STB1 STB4 STB3 STB2 SRI IN CLK INPUT 12-BIT SHIFT REGISTER OUT SRO AGND
DAC REGISTER LOAD
DGND
The DAC8143 is a 12-bit serial-input daisy-chain CMOS D/A converter that features serial data input and buffered serial data output. It was designed for multiple serial DAC systems, where serially daisy-chaining one DAC after another is greatly simplified. The DAC8143 also minimizes address decoding lines enabling simpler logic interfacing. It allows three-wire interface for any number of DACs: one data line, one CLK line and one load line. Serial data in the input register (MSB first) is sequentially clocked out to the SRO pin as the new data word (MSB first) is simultaneously clocked in from the SRI pin. The strobe inputs are used to clock in/out data on the rising or falling (user selected) strobe edges (STB1, STB2, STB3, STB4). When the shift register's data has been updated, the new data word is transferred to the DAC register with use of LD1 and LD2 inputs. Separate LOAD control inputs allow simultaneous output updating of multiple DACs. An asynchronous CLEAR input resets the DAC register without altering data in the input register. Improved linearity and gain error performance permits reduced circuit parts count through the elimination of trimming components. Fast interface timing reduces timing design considerations while minimizing microprocessor wait states. The DAC8143 is available in plastic packages that are compatible with autoinsertion equipment. Plastic packaged devices come in the extended industrial temperature range of -40C to +85C. REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
WR ADDRESS BUS
ADDRESS DECODER
DBX
SRI
STROBE
SRO LOAD P SRI
DAC8143
STROBE
SRO LOAD
DAC8143
SRI
STROBE
SRO LOAD
DAC8143
SRI
STROBE
SRO LOAD
DAC8143
Figure 1. Multiple DAC8143s with Three-Wire Interface
DAC8143-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter STATIC ACCURACY Resolution Nonlinearity Differential Nonlinearity1 Gain Error2 Gain Tempco (Gain/Temp)3 Power Supply Rejection Ratio (Gain/VDD) Output Leakage Current4 Zero Scale Error5, 6 Input Resistance7 AC PERFORMANCE Output Current Settling Time3, 8 AC Feedthrough Error (VREF to IOUT1)3, 9 Digital-to-Analog Glitch Energy3, 10 Total Harmonic Distortion3 Output Noise Voltage Density3, 11 DIGITAL INPUTS/OUTPUT Digital Input HIGH Digital Input LOW Input Leakage Current12 Input Capacitance Digital Output High Digital Output Low ANALOG OUTPUTS Output Capacitance3 Output Capacitance3 TIMING CHARACTERISTICS3 Serial Input to Strobe Setup Times (tSTB = 80 ns) Symbol N INL DNL GFSE TCGFS PSRR ILKG IZSE RIN tS FT Q THD en VIH VIL IIN CIN VOH VOL COUT1 COUT2 COUT1 COUT2 tDS1 tDS2 tDS3 tDS4 tDH1 tDH2 Serial Input to Strobe Hold Times (tSTB = 80 ns) VREF = 20 V p-p @ f = 10 kHz, TA = +25C VREF = 0 V, IOUT Load = 100 , CEXT = 13 pF VREF = 6 V rms @ 1 kHz DAC Register Loaded with All 1s 10 Hz to 100 kHz Between RFB and IOUT 2.4 VIN = 0 V to +5 V VIN = 0 V IOH = -200 A IOL = 1.6 mA Digital Inputs = All 1s Digital Inputs = All 0s Digital Inputs = All 0s Digital Inputs = All 1s STB1 Used as the Strobe STB2 Used as the Strobe STB3 Used as the Strobe TA = +25C TA = Full Temperature Range STB4 Used as the Strobe STB1 Used as the Strobe TA = +25C TA = Full Temperature Range STB2 Used as the Strobe TA = +25C TA = Full Temperature Range STB3 Used as the Strobe STB4 Used as the Strobe 50 20 10 20 20 40 50 50 60 80 80 0.8 1 8 4 0.4 90 90 60 60 VDD = 5% TA = +25C TA = Full Temperature Range TA = +25C TA = Full Temperature Range VREF Pin
(@ VDD = +5 V; VREF = +10 V; VOUT1 = VOUT2 = VAGND = VDGND = 0 V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)
Conditions Min 12 1 1 2 5 0.0006 0.002 5 25 0.002 0.03 0.01 0.15 11 15 0.380 1 2.0 20 -92 13 Typ Max Units Bits LSB LSB LSB ppm/C %/% nA nA LSB LSB k s mV p-p nVs dB nV/Hz V V A pF V V pF pF pF pF ns ns ns ns ns ns ns ns ns ns ns
7
tDH3 tDH4
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DAC8143 ELECTRICAL CHARACTERISTICS
Parameter STB to SRO Propagation Delay
13
(@ VDD = +5 V; VREF = +10 V; VOUT1 = V0UT2 = VAGND = VDGND = 0 V; TA = Full Temperature Range specified under Absolute Maximum Ratings, unless otherwise noted.)
Symbol tPD tSRI tSTB1 tSTB2 tSTB3 tSTB4 tLD1, tLD2 Conditions TA = +25C TA = Full Temperature Range 100 80 80 80 80 140 180 0 80 4.75 All Digital Inputs = VIH or VIL All Digital Inputs = 0 V or VDD Digital Inputs = 0 V or VDD 5 V x 0.1 mA Digital Inputs = VIH or VIL 5 V x 2 mA 5 5.25 2 0.1 0.5 10 Min DAC8143 Typ Max 220 300 Units ns ns ns ns ns ns ns ns ns ns ns V mA mA mW mW
SRI Data Pulsewidth STB1 Pulsewidth (STB1 = 80 ns)14 STB2 Pulsewidth (STB2 = 100 ns)14 STB3 Pulsewidth (STB3 = 80 ns)14 STB4 Pulsewidth (STB4 = 80 ns)14 Load Pulsewidth LSB Strobe into Input Register to Load DAC Register Time CLR Pulsewidth POWER SUPPLY Supply Voltage Supply Current Power Dissipation
TA = +25C TA = Full Temperature Range
tASB tCLR VDD IDD PD
NOTES 11 All grades are monotonic to 12 bits over temperature. 12 Using internal feedback resistor. 13 Guaranteed by design and not tested. 14 Applies to IOUT1; all digital inputs = V IL, VREF = +10 V; specification also applies for I OUT2 when all digital inputs = V IH. 15 VREF = +10 V, all digital inputs = 0 V. 16 Calculated from worst case R REF: IZSE (in LSBs) = (RREF x ILKG x 4096) /VREF. 17 Absolute temperature coefficient is less than +300 ppm/C. 18 IOUT, Load = 100 . CEXT = 13 pF, digital input = 0 V to V DD or VDD to 0 V. Extrapolated to 1/2 LSB: t S = propagation delay (t PD) +9 , where equals measured time constant of the final RC decay. 19 All digital inputs = 0 V. 10 VREF = 0 V, all digital inputs = 0 V to V DD or VDD to 0 V. 11 Calculations from e n = 4K TRB where: K = Boltzmann constant, J/KR = resistance T = resistor temperature, K B = bandwidth, Hz 12 Digital inputs are CMOS gates; I IN typically 1 nA at +25C. 13 Measured from active strobe edge (STB) to new data output at SRO; C L = 50 pF. 14 Minimum low time pulsewidth for STB 1, STB2, and STB4, and minimum high time pulsewidth for STB 3. Specifications subject to change without notice.
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DAC8143
ABSOLUTE MAXIMUM RATINGS
(TA = +25C, unless otherwise noted.)
PIN CONNECTIONS 16-Lead Epoxy Plastic DIP 16-Lead SOIC
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V VREF to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VRFB to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3 V Digital Input Voltage Range . . . . . . . . . . . . . . . -0.3 V to VDD Output Voltage (Pin 1, Pin 2) . . . . . . . . . . . . . . -0.3 V to VDD Operating Temperature Range FP/FS Versions . . . . . . . . . . . . . . . . . . . . . -40C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150C Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C Package Type 16-Lead Plastic DIP 16-Lead SOIC
JA* JC
IOUT1 1 IOUT2 2 AGND 3 STB1 4
16 15 14
RFB VREF VDD CLR
DAC8143
13
TOP VIEW LD1 5 (Not to Scale) 12 DGND SRO 6 11 STB4 SRI 7 STB2 8
10 9
STB3 LD2
Units C/W C/W
76 92
33 27
*JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for P-DIP package; JA is specified for device soldered to printed circuit board for SOIC package.
CAUTION
1. Do not apply voltage higher than VDD or less than DGND potential on any terminal except VREF (Pin 15) and RFB (Pin 16). 2. The digital control inputs are Zener-protected; however, permanent damage may occur on unprotected units from high energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper antistatic handling procedures. 4. Absolute Maximum Ratings apply to packaged devices. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
ORDERING GUIDE
Model DAC8143FP DAC8143FS
Nonlinearity 1 LSB 1 LSB
Gain Error 2 LSB 2 LSB
Temperature Range -40C to +85C -40C to +85C
Package Descriptions 16-Lead Plastic DIP 16-Lead SOIC
Package Options N-16 R-16W
Die Size: 99 x 107 mil, 10,543 sq. mils.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the DAC8143 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Typical Performance Characteristics- DAC8143
ALL BITS ON (MSB) B11 B10 B9 B8 B7 DATA BITS "ON" B6 (ALL OTHER B5 DATA BITS "OFF") B4 B3 B2 B1 (LSB) B0 0 12 24 36 48 60 72 84 96 100 1k 10k 100k FREQUENCY - Hz 1M 108 10M -95 10 100 1k 10k FREQUENCY - Hz 0.0018 100k
ATTENUATION - dB
-70 VIN = 5V rms OUTPUT OP AMP: OP-42 -75
0.032
0.018
THD - dB
-85
0.0056
-90
0.0032
Figure 2. Multiplying Mode Frequency Response vs. Digital Code
Figure 3. Multiplying Mode Total Harmonic Distortion vs. Frequency
3
0.5 0.4
LINEARITY ERROR - LSB
0.5
0.3 0.25 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.25 INL - LSB
2
IDD - mA
0
1
0 0 1 2 3 VIN - Volts 4 5
-0.5
0 512 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE - Decimal
-0.5
2
4
6 VREF - Volts
THD - %
-80
0.010
8
10
Figure 4. Supply Current vs. Logic Input Voltage
Figure 5. Linearity Error vs. Digital Code
Figure 6. Linearity Error vs. Reference Voltage
4
THRESHOLD VOLTAGE - Volts
0.5
40 TA = +25 C 30 LOGIC 0
3 2.4 2
DNL - LSB
0.25
OUTPUT CURRENT - mA SOURCE SINK
20 10 0 -10 LOGIC 1 -20 -30 -40
0
1 -0.8
-0.25
0 1 3 5 7 9 11 VDD - Volts 13 15 17
-0.5
2
4
6 VREF - Volts
8
10
0
1 2 3 4 SRO - VOLTAGE OUT - Volts
5
Figure 7. Logic Threshold Voltage vs. Supply Voltage
Figure 8. DNL Error vs. Reference Voltage
Figure 9. Digital Output Voltage vs. Output Current
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DAC8143
DEFINITION OF SPECIFICATIONS
RESOLUTION
The resolution of a DAC is the number of states (2n) into which the full-scale range (FSR) is divided (or resolved), where "n" is equal to the number of bits.
SETTLING TIME
Time required for the analog output of the DAC to settle to within 1/2 LSB of its final value for a given digital input stimulus; i.e., zero to full-scale.
GAIN
A simplified circuit of the DAC8143 is shown in Figure 10. An inversed R-2R ladder network consisting of silicon-chrome, thin-film resistors, and twelve pairs of NMOS current-steering switches. These switches steer binarily weighted currents into either IOUT1 or IOUT2. Switching current to IOUT1 or IOUT2 yields a constant current in each ladder leg, regardless of digital input code. This constant current results in a constant input resistance at VREF equal to R (typically 11 k). The VREF input may be driven by any reference voltage or current, ac or dc, that is within the limits stated in the Absolute Maximum Ratings chart. The twelve output current-steering switches are in series with the R-2R resistor ladder, and therefore, can introduce bit errors. It was essential to design these switches such that the switch "ON" resistance be binarily scaled so that the voltage drop across each switch remains constant. If, for example, Switch 1 of Figure 10 was designed with an "ON" resistance of 10 , Switch 2 for 20 , etc., a constant 5 mV drop would then be maintained across each switch. To further ensure accuracy across the full temperature range, permanently "ON" MOS switches were included in series with the feedback resistor and the R-2R ladder's terminating resistor. The Simplified DAC Circuit, Figure 10, shows the location of these switches. These series switches are equivalently scaled to two times Switch 1 (MSB) and top Switch 12 (LSB) to maintain constant relative voltage drops with varying temperature. During any testing of the resistor ladder or RFEEDBACK (such as incoming inspection), VDD must be present to turn "ON" these series switches.
VREF 10k 20k S1 10k 20k S2 20k S3 10k 20k S12 20k
Ratio of the DAC's external operational amplifier output voltage to the VREF input voltage when all digital inputs are HIGH.
FEEDTHROUGH ERROR
Error caused by capacitive coupling from VREF to output. Feedthrough error limits are specified with all switches off.
OUTPUT CAPACITANCE
Capacitance from IOUT1 to ground.
OUTPUT LEAKAGE CURRENT
Current appearing at IOUT1 when all digital inputs are LOW, or at IOUT2 terminal when all inputs are HIGH.
GENERAL CIRCUIT INFORMATION
The DAC8143 is a 12-bit serial-input, buffered serial-output, multiplying CMOS D/A converter. It has an R-2R resistor ladder network, a 12-bit input shift register, 12-bit DAC register, control logic circuitry, and a buffered digital output stage. The control logic forms an interface in which serial data is loaded, under microprocessor control, into the input shift register and then transferred, in parallel, to the DAC register. In addition, buffered serial output data is present at the SRO pin when input data is loaded into the input register. This buffered data follows the digital input data (SRI) by 12 clock cycles and is available for daisy-chaining additional DACs. An asynchronous CLEAR function allows resetting the DAC register to a zero code (0000 0000 0000) without altering data stored in the registers.
*
IOUT2 10k IOUT1 RFEEDBACK
*
BIT 1 (MSB) BIT 2 BIT 3 BIT 12 (LSB) DIGITAL INPUTS (SWITCHES SHOWN FOR DIGITAL INPUTS "HIGH")
*THESE SWITCHES
PERMANENTLY "ON"
Figure 10. Simplified DAC Circuit
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DAC8143
ESD PROTECTION
DYNAMIC PERFORMANCE
ANALOG OUTPUT IMPEDANCE
The DAC8143 digital inputs have been designed with ESD resistance incorporated through careful layout and the inclusion of input protection circuitry. Figure 11 shows the input protection diodes. High voltage static charges applied to the digital inputs are shunted to the supply and ground rails through forward biased diodes. These protection diodes were designed to clamp the inputs well below dangerous levels during static discharge conditions.
VDD
The output resistance, as in the case of the output capacitance, varies with the digital input code. This resistance, looking back into the IOUT1 terminal, varies between 11 k (the feedback resistor alone when all digital input are LOW) and 7.5 k (the feedback resistor in parallel with approximately 30 k of the R-2R ladder network resistance when any single bit logic is HIGH). Static accuracy and dynamic performance will be affected by these variations. The gain and phase stability of the output amplifier, board layout, and power supply decoupling will all affect the dynamic performance of the DAC8143. The use of a small compensation capacitor may be required when high speed operational amplifiers are used. It may be connected across the amplifier's feedback resistor to provide the necessary phase compensation to critically damp the output. The considerations when using high speed amplifiers are: 1. Phase compensation (see Figures 16 and 17). 2. Power supply decoupling at the device socket and use of proper grounding techniques.
OUTPUT AMPLIFIER CONSIDERATIONS
DTL/TTL/CMOS INPUTS
Figure 11. Digital Input Protection
EQUIVALENT CIRCUIT ANALYSIS
Figures 12 and 13 show equivalent circuits for the DAC8143's internal DAC with all bits LOW and HIGH, respectively. The reference current is switched to IOUT2 when all data bits are LOW, and to IOUT1 when all bits are HIGH. The ILEAKAGE current source is the combination of surface and junction leakages to the substrate. The 1/4096 current source represents the constant 1-bit current drain through the ladder's terminating resistor. Output capacitance is dependent upon the digital input code. This is because the capacitance of a MOS transistor changes with applied gate voltage. This output capacitance varies between the low and high values.
RFEEDBACK R = 10k IOUT1 I LEAKAGE I REF R = 10k IOUT2 V REF 1/4096 I LEAKAGE 90pF 60pF
When using high speed op amps, a small feedback capacitor (typically 5 pF-30 pF) should be used across the amplifiers to minimize overshoot and ringing. For low speed or static applications, ac specifications of the amplifier are not very critical. In high speed applications, slew rate, settling time, openloop gain and gain/phase margin specifications of the amplifier should be selected for the desired performance. It has already been noted that an offset can be caused by including the usual bias current compensation resistor in the amplifier's noninverting input terminal. This resistor should not be used. Instead, the amplifier should have a bias current that is low over the temperature range of interest. Static accuracy is affected by the variation in the DAC's output resistance. This variation is best illustrated by using the circuit of Figure 14 and the equation: VERROR = VOS 1+ R O
R VREF R R ETC R2 R2 R2 RFB
RFB
Figure 12. Equivalent Circuit (All Inputs LOW)
RFEEDBACK I REF R = 10k V REF 1/4096 I LEAKAGE 90pF R = 10k IOUT1
OP-77
VOS
IOUT2 I LEAKAGE 60pF
Figure 14. Simplified Circuit
Figure 13. Equivalent Circuit (All Inputs HIGH)
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DAC8143
Where RO is a function of the digital code, and: RO = 10 k for more than four bits of Logic 1, RO = 30 k for any single bit of Logic 1. Therefore, the offset gain varies as follows: at code 0011 1111 1111, VERROR1 = VOS at code 0100 0000 0000,
10 k VERROR2 = VOS 1+ 30 k = 4/3 VOS 10 k 1+ 10 k = 2 VOS
Serial data output (SRO) follows the serial data input (SRI) by 12 clocked bits. Holding any STROBE input at its selected state (i.e., STB1, STB2 or STB4 at logic HIGH or STB3 at logic LOW) will act to prevent any further data input. When a new data word has been entered into the input register, it is transferred to the DAC register by asserting both LOAD inputs. The CLR input allows asynchronous resetting of the DAC register to 0000 0000 0000. This reset does not affect data held in the input registers. While in unipolar mode, a CLEAR will result in the analog output going to 0 V. In bipolar mode, the output will go to -VREF.
INTERFACE INPUT DESCRIPTION
The error difference is 2/3 VOS. Since one LSB has a weight (for VREF = +10 V) of 2.4 mV for the DAC8143, it is clearly important that VOS be minimized, using either the amplifier's pulling pins, an external pulling network, or by selection of an amplifier with inherently low VOS. Amplifiers with sufficiently low VOS include OP77, OP97, OP07, OP27, and OP42.
INTERFACE LOGIC OPERATION
STB1 (Pin 4), STB2 (Pin 8), STB4 (Pin 11)--Input Register and Buffered Output Strobe. Inputs Active on Rising Edge. Selected to load serial data into input register and buffered output stage. See Table I for details. STB3 (Pin 10)--Input Register and Buffered Output Strobe Input. Active on Falling Edge. Selected to load serial data into input register and buffered output stage. See Table I for details. LD1 (Pin 5), LD2 (Pin 9)--Load DAC Register Inputs. Active Low. Selected together to load contents of input register into DAC register. CLR (Pin 13)--Clear Input. Active Low. Asynchronous. When LOW, 12-bit DAC register is forced to a zero code (0000 0000 0000) regardless of other interface inputs.
The microprocessor interface of the DAC8143 has been designed with multiple STROBE and LOAD inputs to maximize interfacing options. Control signals decoding may be done on chip or with the use of external decoding circuitry (see Figure 21). Serial data is clocked into the input register and buffered output stage with STB1, STB2, or STB4. The strobe inputs are active on the rising edge. STB3 may be used with a falling edge clock data.
WORD N -1
WORD N
SRI
BIT 1 MSB
BIT 2
BIT 12 LSB
BIT 1 MSB
BIT 2
BIT 11
BIT 12 LSB
tDH1, tDH2, tDH3, tDH4 tDS1, tDS2, tDS3, tDS4
BIT 1 MSB WORD N -2 BIT 2 BIT 1 MSB
tSR1
WORD N -1 BIT 2 BIT 12 LSB WORD N BIT 1 LSB
SRO
tPD * STROBE (STB1, STB2, STB4) tSTB1 tSTB2 tSTB3 tSTB4
LD1 AND LD2 LOAD NEW 12-BIT WORD INTO INPUT REGISTER AND SHIFT OUT PREVIOUS WORD NOTES: * STROBE WAVEFORM IS INVERTED IF STB3 IS USED TO STROBE SERIAL DATA BITS INTO INPUT REGISTER. ** DATA IS STROBED INTO AND OUT OF THE INPUT SHIFT REGISTER MSB FIRST. 1 2 12 1 2 11 12
tSTB1 tSTB2 tSTB3 tSTB4
tASB
tLD1 tLD2
LOAD INPUT REGISTER'S DATA INTO DAC REGISTER
Figure 15. Timing Diagram
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DAC8143
Table I. Truth Table
DAC8143 Logic Inputs Input Register/ Digital Output Control Inputs STB4 STB3 STB2 STB1
0 0 0 g 1 X X X 1 1 f 1 X 0 X X 0 g 0 0 X X 1 X g 0 0 0 X X X 1
DAC Register CLR
X X X X
Control Inputs LD2 LD1
X X X X X X X X
DAC8143 Operation
Serial Data Bit Loaded from SRI into Input Register and Digital Output (SRO Pin) after 12 Clocked Bits. No Operation (Input Register and SRO)
Notes
2, 3
3
0 1 1 1
X 1 X 0
X X 1 0
Reset DAC Register to Zero Code (Code: 0000 0000 0000) (Asynchronous Operation) No Operation (DAC Register and SRO) Load DAC Register with the Contents of Input Register
1, 3 3 3
NOTES 1 CLR = 0 asynchronously resets DAC Register to 0000 0000 0000, but has no effect on Input Register. 2 Serial data is loaded into Input Register MSB first, on edges shown. g is positive edge, f is negative edge. 3 0 = Logic LOW, 1 = Logic HIGH, X = Don't Care.
APPLICATIONS INFORMATION
UNIPOLAR OPERATION (2-QUADRANT)
The circuit shown in Figures 16 and 17 may be used with an ac or dc reference voltage. The circuit's output will range between 0 V and +10(4095/4096) V depending upon the digital input code. The relationship between the digital input and the analog output is shown in Table II. The VREF voltage range is the maximum input voltage range of the op amp or 25 V, whichever is lowest.
Table II. Unipolar Code Table
VREF -10V CLR
+5V VREF 15 13 4, 5 14 VDD RFEEDBACK 15pF 1 2 3 6 12 SRO (BUFFERED DIGITAL DATA OUT) I OUT1 I OUT2 AGND 3 2 OP-77 4 -15V +15V 7 6 VOUT
CONTROL INPUTS
DAC8143
8-11
SRI (SERIAL DATA IN)
7
Digital Input MSB LSB
1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
Nominal Analog Output (VOUT as Shown in Figures 16 and 17) 4095 -VREF 4096 -VREF -VREF -VREF -VREF -VREF
2049 4096 VREF 2048 4096 = - 2 2047 4096 1 4096 0 4096 = 0
DGND
Figure 16. Unipolar Operation with High Accuracy Op Amp (2-Quadrant)
VREF -10V
R1 100 VREF
+5V VDD 14 I OUT1 I OUT2 AGND 3 R2 50 15pF 2 OP-42 4 -15V +15V 7 6 VOUT RFEEDBACK
CLR
15 13 4, 5
1 2 3 12 6
CONTROL INPUTS
DAC8143
8-11
SRI (SERIAL DATA IN)
7
NOTES 1 Nominal full scale for the circuits of Figures 16 and 17 is given by FS = -VREF
2
DGND
SRO (BUFFERED DIGITAL DATA OUT)
4095 4096 .
1
Figure 17. Unipolar Operation with Fast Op Amp and Gain Error Trimming (2-Quadrant)
Nominal LSB magnitude for the circuits of Figures 16 and 17 is given by LSB = VREF 4096 or VREF(2-n).
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DAC8143
In many applications, the DAC8143's zero scale error and low gain error, permit the elimination of external trimming components without adverse effects on circuit performance. For applications requiring a tighter gain error than 0.024% at 25C for the top grade part, or 0.048% for the lower grade part, the circuit in Figure 17 may be used. Gain error may be trimmed by adjusting R1. The DAC register must first be loaded with all 1s. R1 is then adjusted until VOUT = -VREF (4095/4096). In the case of an adjustable VREF, R1 and RFEEDBACK may be omitted, with VREF adjusted to yield the desired full-scale output.
BIPOLAR OPERATION (4-QUADRANT) Table III. Bipolar (Offset Binary) Code Table
Digital Input MSB
LSB
Nominal Analog Output (VOUT as Shown in Figure 18) +VREF 2048 +VREF 2048 0 -VREF 2048 -VREF 2048 -VREF 2048
2048 1 1 2047
1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000
2047
Figure 18 details a suggested circuit for bipolar, or offset binary, operation. Table III shows the digital input-to-analog output relationship. The circuit uses offset binary coding. Twos complement code can be converted to offset binary by software inversion of the MSB or by the addition of an external inverter to the MSB input. Resistor R3, R4 and R5 must be selected to match within 0.01% and must all be of the same (preferably metal foil) type to assure temperature coefficient match. Mismatching between R3 and R4 causes offset and full-scale error. Calibration is performed by loading the DAC register with 1000 0000 0000 and adjusting R1 until VOUT = 0 V. R1 and R2 may be omitted by adjusting the ratio of R3 to R4 to yield VOUT = 0 V. Full scale can be adjusted by loading the DAC register with 1111 1111 1111 and adjusting either the amplitude of VREF or the value of R5 until the desired VOUT is achieved.
NOTES 1 Nominal full scale for the circuits of Figure 18 is given by 2047 FS = VREF . 2048
2
Nominal LSB magnitude for the circuits of Figure 18 is given by
1 LSB = VREF . 2048
DAISY-CHAINING DAC8143s
Many applications use multiple serial input DACs that use numerous interconnecting lines for address decoding and data lines. In addition, they use some type of buffering to reduce loading on the bus. The DAC8143 is ideal for just such an application. It not only reduces the number of interconnecting lines, but also reduces bus loading. The DAC8143 can be daisychained with only three lines: one data line, one CLK line and one load line, see Figure 19.
+5V 14 12 15 R1 100 SERIAL DATA INPUT 7 DGND VREF VDD 15 RFB
R2 50 C1 10-33pF IOUT1 1 A1 1/2 OP200 R3 10k
R4 20k
R5 20k
VIN
DAC8143
IOUT2 CLR SRO 13 6 AGND 4, 5
CONTROL SRI BITS
2 3
A2 1/2 OP200
VOUT
8-11
COMMON GROUND BUFFERED SERIAL DATA OUT FROM SYSTEM RESET CONTROL INPUTS
Figure 18. Bipolar Operation (4-Quadrant, Offset Binary)
-10-
REV. C
DAC8143
APPLICATION TIPS
ADDRESS BUS
WR
ADDRESS DECODER
DBX
SRI
STROBE
SRO P
DAC8143
LOAD
In most applications, linearity depends on the potential of IOUT1, IOUT2, and AGND (Pins 1, 2 and 3) being exactly equal to each other. In most applications, the DAC is connected to an external op amp with its noninverting input tied to ground (see Figures 16 and 17). The amplifier selected should have a low input bias current and low drift over temperature. The amplifier's input offset voltage should be nulled to less than 200 V (less than 10% of 1 LSB). The operational amplifier's noninverting input should have a minimum resistance connection to ground; the usual bias current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The VDD power supply should have a low noise level with no transients greater than +17 V. It is recommended that the digital inputs be taken to ground or VDD via a high value (1 M) resistor; this will prevent the accumulation of static charge if the PC card is disconnected from the system. Peak supply current flows as the digital input pass through the transition region (see Figure 4). The supply current decreases as the input voltage approaches the supply rails (VDD or DGND), i.e., rapidly slewing logic signals that settle very near the supply rails will minimize supply current.
INTERFACING TO THE MC6800
SRI
STROBE
SRO LOAD
DAC8143
SRI
STROBE
SRO
DAC8143
LOAD
SRI
STROBE
SRO LOAD
DAC8143
Figure 19. Multiple DAC8143s with Three-Wire Interface
ANALOG/DIGITAL DIVISION
The transfer function for the DAC8143 connect in the multiplying mode as shown in Figures 16 and 17 is: VO = -VIN
A1 A2 A3 A12 21 + 2 2 + 2 3 + ... 2 12
where AX assumes a value of 1 for an "ON" bit and 0 for an "OFF" bit. The transfer function is modified when the DAC is connected in the feedback of an operational amplifier as shown in Figure 20 and is:
-VIN VO = A1 A2 A3 A12 + + 3 + ... 21 22 2 212
As shown in Figure 21, the DAC8143 may be interfaced to the 6800 by successively executing memory WRITE instruction while manipulating the data between WRITEs, so that each WRITE presents the next bit. In this example, the most significant bits are found in memory locations 0000 and 0001. The four MSBs are found in the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB7 line. The serial data loading is triggered by STB4 which is asserted by a decoded memory WRITE to a memory location, R/W, and 2. A WRITE to another address location transfers data from input register to DAC register.
A0 A15 MC6800 R/W 2 E1 E3 E2 A0 A2 74LS138 ADDRESS DECODER 16-BIT ADDRESS BUS
The above transfer function is the division of an analog voltage (VREF) by a digital word. The amplifier goes to the rails with all bits "OFF" since division by zero is infinity. With all bits "ON" the gain is 1 ( 1 LSB). The gain becomes 4096 with the LSB, Bit 12, "ON".
DIGITAL INPUTS 4 VIN 16 RFB 13 VDD SRO 14 6 15 +5V BUFFERED DIGITAL DATA OUT
DB0 DB7 8-BIT DATA BUS SRI LD2 STB1 STB3 DAC8143* LD1 SRO STB2 STB4 CLR
DAC8143
1 IOUT1 VREF
+5V
AGND 3
2 12 DGND
FROM SYSTEM RESET
2
- OP-42 6 VOUT
*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY
Figure 21. DAC8143--MC6800 Interface
3+
Figure 20. Analog/Digital Divider
REV. C
-11-
DAC8143
DAC8143 INTERFACE TO THE 8085 DAC8143 INTERFACE TO THE 68000
The DAC8143's interface to the 8085 microprocessor is shown in Figure 22. Note that the microprocessor's SOD line is used to present data serially to the DAC. Data is strobed into the DAC8143 by executing memory write instructions. The strobe 2 input is generated by decoding an address location and WR. Data is loaded into the DAC register with a memory write instruction to another address location. Serial data supplied to the DAC8143 must be present in the right-justified format in registers H and L of the microprocessor.
(8) 8085 ALE WR 8212 +5V E1 E3 E2 (8) AD0-7 DATA A0 A2 74LS138 ADDRESS DECODER ADDRESS BUS (16) A0-A15
Figure 23 shows the DAC8143 configured to the 68000 microprocessor. Serial data input is similar to that of the 6800 in Figure 21.
A1 A23
AS 68000 P VMA
CS
ADDRESS DECODER
+
VPA 1/4 74HC125 UDS
+5V
STB3 STB1 LD2 LD1 STB2 DAC8143 STB4 SRI CLR
FROM SYSTEM RESET DB15 DB0
LD2 STB2
DATA BUS
SOD +5V
SRI
STB3 STB1 DAC8143* SRO STB4 LD1 CLR
Figure 23. DAC8143 to 68000 P Interface
FROM SYSTEM RESET
*ANALOG CIRCUITRY OMITTED FOR SIMPLICITY
Figure 22. DAC8143--8085 Interface
OUTLINE DIMENSIONS
Dimensions are shown in inches and (mm).
16-Lead Plastic DIP (N-16)
0.4133 (10.50) 0.3977 (10.00)
9 8
16-Lead SOIC (R-16W)
0.840 (21.34) 0.745 (18.92)
16 1
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62)
16
9
PIN 1 0.210 (5.33) MAX 0.130 (3.30) 0.160 (4.06) MIN 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) SEATING PLANE (2.54) 0.014 (0.356) BSC 0.045 (1.15)
0.2992 (7.60) 0.2914 (7.40)
1 8
0.195 (4.95) 0.115 (2.93) PIN 1 0.015 (0.381) 0.008 (0.204) 0.050 (1.27) BSC 0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0 PLANE 0.0125 (0.32) 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-12-
REV. C
PRINTED IN U.S.A.
0.4193 (10.65) 0.3937 (10.00)
C3114c-2-3/99
ADDRESS BUS

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